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Analysis and Design of Digital Integrated Circuits, Fall 2003

(Complete Item Description)

Abstract:: Device and circuit level optimization of digital building blocks. MOS and bipolar device models and second order effects. Circuit design styles and arithmetic structures. Estimation and minimization of energy consumption. Interconnect models and parasitics; driver design; timing issues (clock skew, self-timed circuits, etc.). Memory architectures, circuits (sense amplifiers) and devices. Testing of integrated circuits. Extensive use of circuit layout and SPICE in design projects and software labs.

Subject:: Science and Technology
Grade Level:: Post-secondary
Collection:: MIT OpenCourseWare

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Top Keywords

Avanwaves Circuit Design Clock Distribution Techniques Clock Skew CMOS Inverter Combinational Logic Computer Sciences Deep Sub-Micron Effects Device Level Optimization Device Sizing Digital Integrated Circuit Electrical Engineering HSPICE Interconnect Models Jitter LOGIC Magic Memory Architectures Mos Nanosim Parasitics Sense Amplifiers Sequential Circuits SPICE Timing

Conditions of Use

No Strings Attached
Remix and Share
Share Only
Read the Fine Print

No restrictions on your remixing, redistributing, or making derivative works. Give credit to the author, as required.

Your remixing, redistributing, or making derivatives works comes with some restrictions, including how it is shared.

Your redistributing comes with some restrictions. Do not remix or make derivative works.

Copyrighted materials, available under Fair Use and the TEACH Act for US-based educators, or other custom arrangements. Go to the resource provider to see their individual restrictions.

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