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Theory of Parallel Hardware (SMA 5511), Spring 2004

(Complete Item Description)

Abstract:: 6.896 covers mathematical foundations of parallel hardware, from computer arithmetic to physical design, focusing on algorithmic underpinnings. Topics covered include: arithmetic circuits, parallel prefix, systolic arrays, retiming, clocking methodologies, boolean logic, sorting networks, interconnection networks, hypercubic networks, P-completeness, VLSI layout theory, reconfigurable wiring, fat-trees, and area-time complexity.

Subject:: Science and Technology
Grade Level:: Post-secondary
Collection:: MIT OpenCourseWare

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Top Keywords

Algorithms Area-Time Complexity Arithmetic Circuits Boolean Logic Clocking Methodologies Computer Arithmetic Computer Sciences Electrical Engineering Fat-Trees Hypercubic Networks Interconnection Networks P-Completeness Parallel Hardware Parallel Prefix Physical Design Reconfigurable Wiring Retiming Sorting Networks Systolic Arrays VLSI Layout Theory

Conditions of Use

No Strings Attached
Remix and Share
Share Only
Read the Fine Print

No restrictions on your remixing, redistributing, or making derivative works. Give credit to the author, as required.

Your remixing, redistributing, or making derivatives works comes with some restrictions, including how it is shared.

Your redistributing comes with some restrictions. Do not remix or make derivative works.

Copyrighted materials, available under Fair Use and the TEACH Act for US-based educators, or other custom arrangements. Go to the resource provider to see their individual restrictions.

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